The present invention relates to a method of fabricating a semiconductor device and, in particular, to a method of fabricating a non-volatile, programmable read-only semiconductor memory device in which each memory transistor has a floating gate.
In a semiconductor memory of this type, electrical isolation between adjacent memory elements has been ordinarily performed by using a selective-oxidation film. It is well-known, however, that memory elements can not be formed with a fine pattern (i.e., the device can not be fabricated at high integration density), due to a so-called bird's beak of selective oxidation film.
In order to solve this problem, a trench isolation structure has been proposed to isolate memory elements from each other, as disclosed in an article by K. Sekiya et al and entitled, "Trench Self-Aligned EPROM Technology", Symposium on VLSI Technology Technical Digest, 1986, pp. 87-88. A method of fabricating a floating gate type PROM using the proposed trench isolation will be described briefly with reference to FIG. 9.
As shown in FIG. 9A, formed on a P type (100-surface) silicon wafer 1 having P well 2 are a gate SiO.sub.2 film 3 having thickness of 350 .ANG., a polysilicon (called hereinafter "poly-Si") film 4 having a thickness of 2000 .ANG. as a floating gate, a SiO.sub.2 film 5 as a mask layer, and a poly-Si film 6 having a thickness of 4000 .ANG. as a spacer. The selective etching by the reactive-ion-etching (RIE) technique is then used to form trenches 8A and 8B, each having a width of 0.9 .mu.m and a depth of 0.4 .mu.m. Thereafter, boron is implanted into the substrate 1 through the trenches 8A and 8B in order to form channel stopper regions (not shown).
Then, by thermal oxidation, as shown in FIG. 9B, a SiO.sub.2 film 7 is formed over the entire surface of the wafer, including the trenches 8A and 8B and, a thick SiO.sub.2 film 9 is then formed by CVD (Chemical Vapor Deposition) to fill the trenches 8A and 8B.
Then, as shown in FIG. 9C, the CVD SiO.sub.2 film 9 is etched back by RIE until a surface of the spacer poly-Si film 6 is exposed.
This RIE is continued until the spacer poly-Si film 6 is removed. Then, the mask SiO.sub.2 film 5 on the poly-Si film 4 is removed by wet etching, resulting in the structure shown in FIG. 9D.
Then, as shown in FIG. 9E, a second gate SiO.sub.2 film 10 having thickness of 200 .ANG. is thermally grown on the poly-Si film 4, followed by forming a poly-Si film 11 as a control gate on the film 10.
Thus, the respective memory elements are isolated by the trenches with a maintaining of the flatness of the wafer surface.
It is well known that the thermally oxidized SiO.sub.2 film 7 on the spacer poly-Si film 6 is etched by RIE at a speed which is lower than the speed of the CVD SiO.sub.2 film 9 deposit. Therefore, the CVD SiO.sub.2 film 9 and the thermal oxidation SiO.sub.2 film 7 in the trenches 8A and 8B may produce a relatively large step as shown in FIG. 9C when the spacer poly-Si film 6 is exposed. In order to remove this step, both of the spacer poly-Si film 6 and the CVD SiO.sub.2 film 9 are etched by RIE, since the etching rate of the film 6 is higher than the etching rate of film 9. The wet etching is then carried out to remove the mask SiO.sub.2 film 5. As a result, the flat surface is obtained as shown in FIG. 9D. Since the mask SiO.sub.2 film 5 is damaged during the etching of the spacer poly-Si film 6, it must be removed.
In the PROM mentioned above, the memory elements are isolated from each other by the trenches and a surface flatness is realized. However, the trenches 8 are filled with the CVD SiO.sub.2 film 9. The CVD SiO.sub.2 film may efficiently fill a trench having a so-called aspect ratio which is representative of a trench depth/trench width, of 0.5 or less. As mentioned above, the trench depth and trench width are 0.4 .mu.m and 0.9 .mu.m, respectively, and thus the aspect ratio is 0.44. Therefore, the trench can be filled effectively with the CVD SiO.sub.2 film 9. However, this process requires that the aspect ratio of the trench to be made large for the following reasons:
(1) The trench width is preferred to be as small as possible in order to increase the integration density of the PROM in a chip.
(2) The trench depth must be increased with a decrease of trench width in order to prevent the occurrence of the parasitic MOS structure. FIG. 10 shows a relationship between the trench width, trench depth and the threshold voltage of the parasitic MOS structure.
On the other hand, the CVD SiO.sub.2 film hardly fills the trench, in particular, the bottom of a trench when the aspect ratio becomes 0.5 or more. For example, with the aspect ratio of 2.0, a void 27 may be formed in the trench as shown in FIG. 11. As a material suitable to fill a trench having the large aspect ratio, Boro-Phospho-Silicate Glass (BPSG) containing silicon oxide, phosphorus and boron is known in the art. Moreover, the BPSG film has a reflow characteristic. Therefore, by using BPSG, the trenches 8 can be completely filled with BPSG while realizing the flatness of the surface.
However, if BPSG is used to fill the trench 8, the phosphorus and boron contained in BPSG are evaporated by the heat treatment for forming the gate SiO.sub.2 film 10 and a portion of the evaporated phosphorus and/or boron is taken into the gate SiO.sub.2 film 10 (see FIG. 9E). Such a gate film degrades the characteristics and the reliability of each PROM cell transistor.